Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, October 1 , 12:00-1:00 p.m. HH-1112


Emrah Acar
IBM Austin Research Laboratory

Leakage Modeling and Analysis for High-Performance Circuits

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate the system power. In the first half of the talk we discuss current techniques for leakage estimation. A static probabilistic technique will be presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predicts both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.

In the second part of the talk, we will discuss the dependency of leakage on operating temperature and power supply voltage (VDD). We will present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profiles are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

Emrah Acar received the B.S. and M.S. degrees in electrical engineering from Bilkent University, Turkey in 1995 and 1997, respectively. He received his Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA in 2001. While pursuing his Ph.D. study, he interned at Strategic CAD Labs at Intel, Hillsboro, Oregon, Compaq Alpha Design Center in Shrewsbury, MA, and IBM Austin Research Laboratory in Austin, TX. He is currently a research staff member at IBM Austin Research Laboratory. His research interests include circuit simulation, timing analysis, low-power design, and statistical analysis.