Thomas Zanon Carnegie Mellon University

Evidence of Layout-Dependent Failure Mechanisms in SRAMs

Layout-dependent failure mechanisms in integrated circuits can be defined as causes for circuit failures influenced by layout geometry. This distinctly differentiates them from failure mechanisms like particulate contaminations, whose origins are independent of any underlying layout. Due to continuously increasing layout-process interaction, driven by shrinking layout feature sizes and more complex processes, the importance of layout-dependent failure mechanisms is expected to grow in future IC technologies. Therefore, detection, understanding and modeling of these failure mechanisms are going to play (and in several cases already play) a significant role for any IC manufacturing venture.

In this talk I demonstrate how layout-dependent failure mechanisms can be detected via analysis of test data of large static memories. Although this approach does not always allow unique identification of specific layout-dependent failure mechanisms, the presented results clearly demonstrate their existence in the analyzed SRAM test vehicle.

Bio
Thomas Zanon received his Dipl.Ing. in Electrical Engineering from the Technical University of Munich in 1996. In 1997 he worked as a research assistant at the Institute for Technical Electronics, Technical University of Munich. Since 1998, he is working for his Ph.D. degree at Carnegie Mellon University with Prof. W. Maly as advisor. His research interests are Technology CAD and failure analysis with focus on understanding failure mechanisms of ULSI systems.