Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, April 16, 12:00-1:00 p.m. HH-1112

David Whelihan
Carnegie Mellon University

Packet Switched Interconnection Networks for SOC

As we move into the billion transistor per chip era, more and more functionality is being moved onto a single chip. These systems are conglomerations of discrete macro-scale blocks (DSPs, RISC processors, memories, etc.) with the associated glue logic to facilitate intercommunication.

Unfortunately, full-chip timing in this environment is non-trivial. It has been estimated that by 2010, on-chip speeds could reach up to 10 GHz. A large System on a Chip with a die edge of 22mm would have a diagonal signal flight time of greater than a clock period. Current ASIC design methodologies will prove inadequate in guaranteeing timing between blocks in such an environment

In this talk, I discuss statically and dynamically routed interconnection networks that facilitate communication between blocks using packet switching. These networks could allow for regularity of communication between blocks, speeding up design cycles.

David Whelihan received his B.S. in Computer Engineering from Syracuse University in 1996. After a 3 year stint as a chip designer, he came to Carnegie Mellon, earning his M.S. in Electrical & Computer Engineering in 2001. His research interests include interconnection networks, and novel reconfigurable devices.