Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, May 28, 12:00-1:00 p.m. HH-1112

Girish Varatkar
Carnegie Mellon University

Modeling and Synthesis of On-Chip Multimedia Traffic

In this talk we address the fundamental issue of optimal buffer sizing between different on-chip modules. For complex systems composed of many heterogeneous components, the on-chip traffic produced among different modules has very diverse characterisitics. Since the traffic patterns depend so much on the target application, it is necessary to judiciously allocate the on-chip communication resources, especially since the on-chip buffer space is usually very limited compared to real data networks. The objective of this talk is to introduce self-similarity as a fundamental property exhibited by the bursty traffic behavior between on-chip modules in typical MPEG-2 video applications. Statistical tests performed on relevant traces extracted from common video clips establish unequivocally the existence of self-similarity in on-chip video traffic. Using a generic on-chip communication architechture, we analyze the implications of self-similar traffic on on-chip buffer space allocation and present quantitative evaluations for typical video streams. In order to speedup the buffer simulation, we propose a technique for synthetically generating traces having statistical properties similar to those obtained from real video clips. We believe that our findings open up new directions of research with deep implications on some fundamental issues in on-chip network design for multimedia applications.

Girish Varatkar is a graduate student in the ECE department at Carnegie Mellon, advised by Professor Radu Marculescu. He received his bachelors in Electrical Engineering in 2001 from the Indian Institute of Technology, Bombay. His research interests are in the system level design of next generation SOC, particularly focusing on the on-chip communication aspects.