Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, February 19, 12:00-1:00 p.m. HH-1112

Noppanunt Utamaphethai
Carnegie Mellon University

Simulation-based Microarchitecture Verification

Design verification is increasingly a bottleneck in processor development cycle due to the processor's size and complexity. A number of techniques ranging from formal methods to simulation-based approaches are employed in order to ensure the correctness of a design.

Simulation is a common tool used by the designers to observe the behavior of a system. It is logical for design verification to rely on simulation of test stimuli on the simulatable model of the design. In this talk, I will briefly review current simulation-based verification techniques. Then, I will present our verification methodology called Buffer-Oriented Microarchitecture Verification (BMV). In BMV, we systematically derive assembly test programs to exercise the control aspect of a processor. The BMV methodology has been applied to an industrial superscalar processor, the PowerPC 604. Simulation results show that BMV-generated test programs are at least two orders of magnitude smaller than randomly-generated programs while providing far better coverage.

Noppanunt Utamaphethai is a Ph.D. candidate in the ECE department, Carnegie Mellon University. He received his Bachelor's degree from Brown University in 1995 and Master's degree in ECE from Carnegie Mellon University in 1997. His research interests are computer architecture, digital system design and verification.