Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, March 26, 12:00-1:00 p.m. HH-1112

Matt Moe
Carnegie Mellon University

Floorplanning for Pipelined Arrays using Sequence Pairs

As feature sizes shrink each year and a half, the contribution of wire delay to total delay increases. Synthesis and place and route tools and methodologies need to be modified so that this new reality is reflected.

Sequence pairs have been used for the past six years as an efficient means of representing any floorplan. Simulated annealing efforts that use sequence pairs either focus entirely on area or use well defined hard blocks where pin locations, and therefore wires, can be easily determined.

This talk will present a new simulated annealing methodology for floorplanning that targets pipelined arrays. A new wire delay metric for soft blocks will be introduced that is based on the longest realistic wire path found between two pipeline stages. A new move set for sequence pairs will also be presented that reduces the annealing design space.

Matt Moe received his B.S. and M.S. in Electrical and Computer Engineering from Carnegie Mellon University in 1996 and 1998 respectively. His previous research work was in architecture for the PipeRench project. His research interests lie throughout the CAD realm (well, everything but Testing and Manufacturing).