Ben Levine Carnegie Mellon University

Queue Machines: Hardware and Software to Enable Integration of Processors and Reconfigurable Fabrics

Reconfigurable computing (RC) has shown great potential to provide flexible, high-performance computational hardware, but it has not been widely adopted. Many of the barriers to the use of RC hardware occur because typical RC systems need a conventional processor in addition to the reconfigurable component. This requires development of two or more separate executables, as well as substantial effort to design interface code and hardware. The executables are specific to the particular hardware used, making portability and performance scaling nearly impossible.

This talk will present a novel architectural paradigm which allows a single executable to run on both a serial processor and on reconfigurable fabrics. Using a queue-based application representation allows for runtime compilation in hardware of serial code into configuration data. This allows both types of hardware to share general processor resources and a single programming model. An explanation of what queue-based application models and architectures are will be presented, as well as some details of how a queue machine architecture could be implemented.

Bio
Ben Levine received his BS in 1997 and his MS in 1999, both in Electrical Engineering, from the University of Tennessee, Knoxville (Go Vols!). He is working on his Ph.D. in ECE at CMU, advised by Professor Herman Schmit, and he is an IBM/SRC Graduate Fellow. He has worked on the PipeRench project at CMU and is collaborating with Northrop Grumman engineers to investigate the implementation of their SAR target recognition applications on PipeRench. His Ph.D. thesis involves the design and performance of queue-based architectures.