Anoop Iyer Carnegie Mellon University

Microarchitecture Level Power Management

Due to large design sizes and leakage currents, power consumption is a major problem in microprocessor designs today. Traditional approaches to reduce power consumption work mostly at the system level (e.g. ACPI) or at the circuit level (e.g. low power gate libraries).

In this talk, I will present a microarchitecture level approach to power management which uses run-time code-profiling hardware. Based on the power and performance profile of the running application, various micro-architectural resources of the processor can be scaled up or down when required. Using this approach, we get good savings in power consumption with minimal loss of performance. This approach is shown to be better than static methods like clock throttling presently used in power management.

Bio
Anoop Iyer is a graduate student in the ECE department at Carnegie Mellon, advised by Prof. Diana Marculescu. He received his bachelors in Electrical Engineering in 2000 from the Indian Institute of Technology, Bombay. His research interests are in computer architecture, low-power computing and VLSI systems.