Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, January 16, 12:00-1:00 p.m. HH-1112

Se-Hyun Yang
Carnegie Mellon University

An Integrated Approach to Reducing Leakage in DSM I-Caches

This talk explores an integrated architectural and circuit-level approach to reduce leakage energy dissipation in instruction caches (i-caches) while maintaining high performance. Using a simple adaptive scheme, we exploit the variability in application demand ina novel cache design, the Dynamically Resizable i-cache (DRI i-cache), by dynamically resizing the cache to the size required at any point in application execution. Simulations using the SPEC95 benchmarks show that a 64K DRI i-cache reduces, on average, both the leakage energy-delay product and average size by 62%, with less than 4% impact on execution time.

Se-Hyun Yang is now pursuing his doctoral degree in the Department of Electrical and Computer Engineering at Carnegie Mellon University. He finished his B.S. and M.S. from Korea Advanced Institute of Science and Technology. His current research interests focus on computer architecture, especially on power-aware microprocessor and memory system design.