Padmini Gopalakrishnan Monterey Design Systems

Wireload Models - The Curse of Top-down Design

The advent of deep sub-micron technologies has created a number of problems for existing design methodologies. Most prominent among them is the problem of timing closure, whereby design time is dramatically increased due to iterations between gate-level synthesis and physical design. It is well known that the heart of this problem lies in the use of wireload models based on wirelength statistics from legacy designs. Some technology projections have suggested that wireload models will remain effective to block sizes on the order of 50k gates. This suggests that synthesis will not have to be changed much since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on actual designs show that the problem is not quite so straightforward, and the efficacy of synthesis using wireload models depends upon technology data as well as specific characteristics of the design. In this talk, we present detailed analyses of these dependencies. We then draw some conclusions about the amount of physical information that is required for synthesis to be effective.

Bio
Padmini Gopalakrishnan is currently on the R&D team at Monterey Design Systems in Sunnyvale, CA. Her research interests are physical synthesis, interconnect estimation and analysis, floorplanning, placement, and design flows and methodologies. She holds a B.Tech. in Electrical Engineering from the Indian Institute of Technology, Madras and an M.S. in Electrical & Computer Engineering from the University of Texas at Austin.