Phil Nigh IBM Senior Engineer

Shipping High-Quality ICs in the Future of GHz, Nanometers, Amps, Watts and Miles of Copper

In this talk, I will discuss changes in technology that are forcing us to change the way we test ICs. Key technological barriers that the industry is facing include:

• Testing huge chips (>100M logic gates) with inexpensive testers in short times (<5 seconds), erosion of the effectiveness of reliability screens such as IDDQ and burn-in, and exploiting design-for-test to enable the use of cheap testers.
  
• Using statistical analysis methods of IC test results to improve our understanding of defects and yield loss that allow the creation of “defect dictionaries”.
  
• The changing behavior of defects are forcing us to change our test methods.
  
• Limiting or finding the number of different chips architectures that enable us to ship higher quality products.

Bio
Dr. Phil Nigh received his B.S. from Case Western Reserve University in 1983, an M.S. from Syracuse in 1986, and Ph.D. from CMU in 1990. He has been an IBM employee since 1983-and is an adjunct faculty member of the University of Vermont. He has 12 patents filed or pending and has won two best-paper awards from the International Test Conference. At IBM, he works in test strategy development where he develops test methods for next-generation ICs, diagnosis, design-for-testability, yield learning, and reliability.