Vincent John Mooney III Georgia Institute of Technology

Dynamic Memory Management Unit in Hardware and a Framework for Automatic Generation of Configuration Files for a Custom Software/Hardware RTOS for SoC

This talk will describe the design of hardware able to interact with multiprocessor RTOS software on a System-on-a-Chip (SoC) to provide second-level on-chip memory allocation/de-allocation in a dynamic yet deterministic way. This SoC Dynamic Memory Management Unit (SoCDMMU) can provide worst-case second-level memory allocation in 16 cycles in a four-processor SoC example. This talk will further describe a framework for automatic generation of configuration files for a custom RTOS implemented partially in software and partially in hardware. The hardware units supported include the SoCDMMU and two other units we will briefly describe in the talk. A database code example shows a speedup of 27% when using a custom software/ hardware RTOS as opposed to just software. Furthermore, the speedup is much greater when considering Worst-Case Execution Time (WCET), for example, over 10X speedup in dynamic memory worst-case allocation time when using the SoCDMMU.

Bio
Vincent J. Mooney III received the B.S. degree from Yale University in 1991, where he double majored in E.E. and C.S. He was a member of the 1989 Ivy League Championship football team for Yale. He received his M.S in EE in 1994, M.A. degree in Philosophy in 1997, and Ph.D. in EE in June of 1998 - each from Stanford University. He has worked at Bell Labs (Lucent), Allied Signal Aerospace VLSI Design Group, Hughes Network Systems, and Redwood Design Automation (Cadence). He's currently an Assistant Professor in the School of ECE and an Adjunct Assistant Professor at the College of Computing, both at the Georgia Institute of Technology in Atlanta, GA. His research interests include computer-aided design of integrated circuits with a particular emphasis on hardware-software co-design, real-time operating systems and low power compilers and architectures.