A 4 Channel Analog Front End for ADSL Modems
In this talk, we will describe a four-channel analog front-end integrated circuit, which was developed for the central office modem in ADSL. The talk will commence with a brief overview of ADSL. In particular, we will focus on why board area and power consumption are important considerations for central office equipment. We will follow with the presentation of a 4th order 2-bit sigma delta modulator, which was key to achieving low power and high board density; a brief overview of sigma-delta modulation will be provided. The chip was implemented in 0.35um double poly triple metal CMOS. The power consumption per channel including the transmitter, receiver and voltage reference is 155 milliwatts.
Jack Kenney was born in Springfield, MA in 1960. He received BS degrees from both Providence College and Columbia University in 1984. His first exposure to analog circuit design was at Motorola Corp. where he developed analog front ends for voiceband telephone applications. Jack received an MSECE and Ph.D. from Carnegie Mellon University in 1988 and 1992 respectively. His research included higher-order multi-bit sigma-delta modulators and signal processing for magnetic recording channels. He was on the faculty of the Department of ECE at Oregon State University from 1992 until 1997 where he had achieved the rank of Associate Professor. His other academic positions include Visiting Researcher at the Data Storage Systems Center (DSSC) of the National University of Singapore in Summer 1996, and Visiting Lecturer with the Department of Electrical Engineering at Princeton University in Fall 1999. Jack joined Analog Devices Inc. in Somerset, NJ in Spring 1997. He spent 3 years developing CMOS analog integrated circuits for the ADSL application and is currently designing clock and data recovery circuits for 10GHz fiber optic channels.