Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, May 22, 12:00-1:00 p.m. HH-1112

Prakash Gopalakrishnan
Carnegie Mellon University

Layout from Logic: Standard Cells Or Transistors?


Modern application-specific ICs (ASICs) are designed and laid out as geometric arrangements of logic gates. These gates are stored in libraries, and are referred to generically as ìcellsî. Cells hide many of the difficult geometric and electrical details of the individual transistors in each gate. In this way, they simplify the overall design flow. However, as fab technologies have evolved and circuit design styles become more aggressive, there is a growing concern that cell libraries prevent us from optimizing our designs to their fullest potential. Given a gate-level design, why can't we just go straight to shape-level layout of the transistors?

This talk is about a complete transistor-level layout flow, from logic netlist to final shapes, for blocks of digital combinational logic up to a few thousand transistors in size. The direct transistor-level attack easily accommodates the demands for careful custom sizing necessary in high-speed design, and is also significantly denser than a comparable cell-based layout. The key algorithmic innovations are (a) early identification of essential diffusion-merged MOS device groups called trail clusters, but (b) deferred binding of clusters to a specific shape-level layout until the very end of a multi-phase placement strategy. A commercial router completes the flow. Experiments comparing to a commercial standard cell-level layout flow show that, when flattened to transistors, our tool consistently achieves 100% routed layouts that average 23% less area.

Prakash Gopalakrishnan is working toward a Ph.D. in the Electrical and Computer Engineering department at Carnegie Mellon University under the guidance of Prof. Rob A. Rutenbar. He holds a B.Tech. in Electrical Engineering from the Indian Institute of Technology, Madras and an M.S. in Electrical & Computer Engineering from Carnegie Mellon University. He has interned with IBM, where he worked on wire-planning & wire-load modeling, and with Intel, where he worked on placement/partitioning, cell layout generation & dynamic logic layout. He is currently an employee of Neolinear Inc., Pittsburgh.