Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, May 15, 12:00-1:00 p.m. HH-1112

Dr. Sorin Cotofana
Delft University of Technology
(TU Delft),
The Netherlands

FPGA Augmented TriMedia: A Case Study

In this talk, we will discuss an experiment which aims to assess the potential impact on performance yielded by augmenting a TriMedia/CPU64 processor with a reconfigurable core. We first propose the skeleton of an extension of the TriMedia/CPU64 architecture, which consists of a Reconfigurable Functional Unit (RFU) and the associated instructions. Then, we address the computation of the 8 X 8 IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When implemented on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia (200 MHz) cycles, and occupies 42% of the device. By configuring the 1-D IDCT computing facility on the RFU at application load-time, a 2-D IDCT including all overheads can be computed with the throughput of 1/32 IDCT/cycle. This is an improvement of more than 40% over the standard TriMedia/CPU64.

Dr. Sorin Cotofana is an assistant professor in the Electrical Engineering Department of Delft University of Technology (TU Delft), The Netherlands. He received the MS degree in Computer Science from the "Politehnica" University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology (T.U. Delft), The Netherlands. His work experience is related to structured design of digital systems, design rule checking of IC's layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. His research interests include computer arithmetic, computer architecture, embedded systems, hardware design and functional testing of computer systems, parallel processors, neural networks, and computer aided design.