Electrical & Computer Engineering     |     Carnegie Mellon

Thursday, May 3, 12:30-1:30 p.m. HH-1112

Michael W. Beattie
Carnegie Mellon University

Inductance Modeling and Extraction

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. The first part of this talk will describe the basic concepts of magnetic induction. The concept of partial inductance is introduced to enable modeling of magnetic induction without knowing the actual current return loops in the circuit. This leads to partial element equivalent circuit (PEEC) models in which partial inductance, resistance and capacitive couplings are combined to model the electromagnetic behavior of the interconnect.

The second part of the presentation addresses the issue of how to make these PEEC models efficient enough for simulation or other formsof circuit analysis by removing a sufficient number of mutual inductive couplings while preserving stability and accuracy of the approximate model. A recent approach to this problem will be presented.

Concluding the presentation, hierarchical PEEC models for on-chip interconnect inductance will be introduced. These models can integrate composite long-range inductive interactions in PEEC models efficiently.

Michael W. Beattie is a member of the research staff at the Department of Electrical and Computer Engineering at Carnegie Mellon University. He received the diploma in physics from the University of Bayreuth (Germany) in 1995 and the Ph.D. in electrical and computer engineering from Carnegie Mellon University in 2000.

His research interests include efficient extraction and modeling of electromagnetic interconnect parasitics for on-chip timing and noise analysis.