This area focuses on the process and product design for the newest
technology nodes, i.e., 45nm and below, in which optical lithography
is reaching fundamental limits. The goal is to optimize multiple objectives
such as performance, leakage, power dissipation and finally yield and
reliability. New approaches to ensure manufacturability by co-optimizing
device design, layout and manufacturing process, and test/diagnosis
are being investigated.
New IC process/design/manufacturing paradigm is being developed in CSSI (by professor Maly). This new paradigm uses as basic components two new complimentary p-channel and n-channel Vertical Slit Field Effect transistors VeSFETs. In one of many possible implementations of VeSFET based ICs (VeSTICs) both sides of silicon layer could be used for achieving highly regular interconnect geometry. Figure on the left shows an example of 6T SRAM cell implemented with VeSFETs.