Manufacturing
This area focuses on the process and product design for the newest
technology nodes, i.e., 45nm and below, in which optical lithography
is reaching fundamental limits. The goal is to optimize multiple objectives
such as performance, leakage, power dissipation and finally yield and
reliability. New approaches to ensure manufacturability by co-optimizing
device design, layout and manufacturing process, and test/diagnosis
are being investigated.
 |
Vision of a CMOS-like
inverter that could be constructed using newly-proposed dual
gate Vertical Slit Field Effect Transistors (VeSFETS ) with
n- and -p type channels. VeSFET transistors fabricated with
SOI like manufacturing processes and double-sided interconnect
is theoretically predicted to be 2X to 10X denser, equally
fast, and consuming much less power than equivalent bulk-CMOS
and Fin-FET devices.
|
Area Leader
Researchers
|
