Don Thomas, PhD
- "The Verilog Hardware Description Language," D.E. Thomas and
P.R. Moorby, Springer, Five editions, some have been translated into
Japanese and Mandarin Chinese.
- “Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical
Approach,” J.M. Paul, A. Bobrek, J.E. Nelson, J.J. Pieper, and D.E.
Thomas. DATE 2004.
- “Shared Resource Access Attributes for High-Level Contention Models,” A.
Bobrek, J.M.Paul, and D.E. Thomas, Design Automation Conference,
- “Event-based Re-training of Statistical Contention Models for Heterogeneous
Multiprocessors”, A.Bobrek, J.M.Paul, D.E.Thomas, CODES+ISSS 2007.
- “Simultaneous Synthesis of Buses, Data Mapping and Memory Allocation
for MPSoC”, B.H. Meyer, D.E.Thomas, CODES+ISSS 2007.