Automated Standard Cell Library Analysis for Improved Defect Modeling

Jason Brown

Project

Testing typically considers only a logic-level model of the circuit under test. In complex ICs however, all physical nodes in the layout do not necessarily correspond to logic-level signals. Therefore, modern VLSI failure mechanisms that manifest as complex misbehaviors may not be captured by traditional logic-level models. In order to reduce DPM (defective parts per million shipped), we must identify defects that are likely to occur and derive and model the faulty circuit behaviors that can result. Inductive fault analysis (IFA) techniques [1,2] examine the physical layout of a design to identify potential defect sites. IFA may require a significant amount of computation but provides a more accurate fault list, which consequently improves testing efficiency and product quality. To reduce computational complexity, IFA is typically performed in a Òblack-boxÓ fashion where standard cells are removed from the layout and only inter-cell connections are considered as potential sites for defects. The primary difficulty involved with internal node defects is that their behavior is not easily modeled because an internal node does not always directly map to a logic-level signal. Instead, many internal cell nodes exhibit transistor-level behavior and therefore cannot be captured using traditional logic-level models. This project is focused on created a mapping between internal nodes of a standard cell and the logic level. We use the mapping to identify appropriate activation and error propagation conditions for internal node defects [3].

Selected Highlights

IFA for bridge defects typically ignores internal cell nodes because it is (erroneously) assumed that they comprise a small percentage of the likely sites. However, Figure 1 demonstrates that the percentages of bridge defects and "critical area" (regions of the layout where defects are likely) involving internal cell nodes are significant. For three benchmark designs and one industrial design, an average of nearly 37% of the bridge defect sites identified involve internal nodes of standard cells. These defect sites comprise more than 21% of the total critical area. Thus, many bridge defects are not explicitly analyzed and therefore may go undetected. A fault simulation experiment was performed using the bridge defects identified via IFA and a test set based on stuck-at faults. Figure 2 shows the fault coverage provided by the stuck-at test set. The coverage for defects involving logic-level signals is quite high (84% and 78%) for the two designs examined. However, the coverage for bridge defects involving internal nodes is much lower (62% and 32%). This difference indicates that internal node bridge defects are not being fortuitously detected by stuck-at test patterns and motivates the need for improved defect-based test generation methodologies which is the focus of our current work.