Exploiting Regularity for Inductive Fault Analysis

Jason Brown

Increased manufacturing complexity coupled with the well-known design gap has fueled research in developing new regular circuit fabrics. In particular, researchers at Carnegie Mellon University, the University of California-Berkeley are aggressively pursuing this area of research. The hope is that constraining circuits to have regular structures will increase both manufacturability and predictability so that the time needed to design and implement next-generation designs will be significantly reduced. One aspect of regularity not being examined however is the impact it will have on test and diagnosis. It is likely that regularity will have a very positive impact on both these important tasks.

For example, inductive fault analysis (IFA) is the process of determining which defects are likely to occur in an integrated circuit for a given manufacturing process and abstracting those defects to a higher level for test analysis. In general, physical information, defect statistics, and a list of failure mechanisms are used to perform IFA as illustrated in Figure 1. Physical information includes the number and location of polygons, number of layers, and die area for the design. Defect statistics include defect density data for each failure mechanism. The types of failure mechanisms used are derived from experiences with older technologies and the development of new ones. This list may include bridges, opens, pinholes, etc. IFA uses this information to calculate defect probabilities in order to create a ranked defect list for the design. The derived defect list can be used to improve many aspects of testing including test generation, design-for-test, etc. Although IFA can be accurate in calculating defect probabilities, an enormous amount of computation is typically required to analyze the entire layout for all failure mechanisms. As a result, IFA has been restricted to only the most likely defect types such as bridges. Even for a single defect type however, the time required to extract defect probabilities is still quite significant.

Although IFA is impractical for irregular designs (e.g. standard cell) due to the time required to analyze the overwhelming number of complex patterns found in multi-million gate designs, in a regular design, a very small portion of the layout can be analyzed to determine the likely defects for the entire design, thus making inductive fault analysis viable. Test and diagnosis of a given design can therefore be vastly improved since the likely, specific defects (shorts, opens, etc.) for a given design can be efficiently identified.

We propose a methodology for IFA that exploits the regularity of design. By extracting from a regular circuit as shown in Figure 2, the computation time required to perform inductive fault analysis (IFA) can be significantly reduced. Rather than calculating critical area for an entire layout, the analysis only needs to be done for a small section (i.e. the stamp) of the layout that is repeated throughout the design. As shown in Figure 3, the time required to perform IFA for VPGA designs is greater than the time required for standard ASIC designs. This increase is due to the increased density of signal lines in the layout. The computation time required for larger designs is significant and in some cases, exceeds sixty hours. IFA for the stamp however requires less than 19 minutes. Therefore, by using the information extracted from the stamp, IFA can be performed effectively without a significant amount of computation. Accurate fault probabilities for large designs such as floating point unit and network switch were compiled in less than 19 minutes.