Physically-Aware Test

Narhesh Bhatti

Yen-Tzu Lin

Osei Poku

Project

The single stuck line (SSL) fault model has been widely used as the basis of integrated circuit test. However, as the minimal feature size shrinks and circuit complexity increases, the behavior of defects become harder to predict and can no longer be adequately addressed by tests aimed solely at SSL faults. Other existing fault models target only a subset of possible misbehaviors (e.g., transition, path-delay, and bridge faults). Defects that have unmodeled effects are therefore more likely to escape detection. N-detect tests were proposed to increase defect coverage [1]; they require each SSL fault to be detected at least N times with different "circuit conditions" which traditionally means that the N tests are different with respect to the values applied to the circuit inputs. We believe the effectiveness of N-detect tests can be improved however by constraining the circuit conditions to the physical neighborhood surrounding the line affected by the defect [2]. That is, in physically-aware N-detect testing, the objective is still to detect an SSL fault N times; however, each of the N tests is required to establish a different state (i.e., set of logical values) for the lines that are physically close to the targeted SSL fault.

Selected Highlights

We are in the process of conducting an industrial experiment with LSI Logic to measure the effectiveness of physically-aware test patterns. For a test chip implemented in 90nm technology, our objective is to maximize state coverage for a given test set size constraint. Specifically, given a 10-detect and a 50-detect test set, we generated a CMU test set whose size was equal to that of the 10-detect test set but the number of neighborhood states covered was maximized. The physical neighborhoods for each signal line were obtained through critical area analysis [3]. Using the physical information, we employed a greedy algorithm for selecting a physically-aware N-detect test set from the 50-detect test set. Figure 2 shows a comparison of a 1-detect, 10-detect, 50-detect, and the CMU test set in terms of the number of neighborhood states covered. The total number of physical neighborhood states covered is 3.85 million for the 10-detect test set, while for the CMU test set there are 4.54 million states covered which means 18.04% more unique states are covered by the CMU test set. Our test set also detects 4.74% more faults that satisfy the 10-detect requirement based on neighborhood states. Figure 1 plots the number of faults versus the number of neighborhood states covered for the test sets. The CMU test set detects an equal or greater number of faults (y-axis) for every covered state count (x-axis), indicating the CMU test set is more effective than the traditional 10-detect test set for the neighborhood state metric. The CMU test set is now being used for wafer sort test of the LSI Logic test chips and its effectiveness for both defect detection and diagnosis will be reported in a future publication.