Distinguishing Test Generation for Arbitrary Faults

Narhesh Bhatti

Project

It is now generally accepted that the stuck-at fault model is no longer sufficient for many integrated circuit (IC) test activities. Consequently, test generation for IC failure diagnosis that is based solely on distinguishing stuck-at faults is inadequate, especially for emerging fault types that include opens, multi-line bridges, and "systematics" (i.e., failures that are due to design and fabrication interactions). Approaches that consider other fault types have been proposed but are limited to pre-defined misbehaviors and therefore cannot handle new failure types that arise with next-generation designs and technologies. Our model independent fault diagnosis methodology [1] that uses arbitrary fault types [2] can significantly benefit from a Distinguishing Test Generation (DTG) capability. In this work [3], we have implemented an efficient DTG methodology that can produce tests that distinguish pairs of arbitrary faults.

Selected Highlights

Our approach to DTG extends an existing Boolean satisfiability formulation for single stuck-at faults [4] to accommodate pairs of arbitrary fault types [1]. Figure 1 depicts the overall flow for deriving fault equivalence classes from a set of faults, where an equivalence class is defined here to be a set of faults that cannot be distinguished with reference to a given test set. The initial set of classes is determined by simulating the faults of interest using some incipient test set. Further partitioning of the classes is accomplished by invoking DTG on pairs of faults within a class. DTG continues as long as there exists untried fault pairs. Table 1 shows the number of classes (column 3) for transistor stuck-open faults for a set of benchmark circuits (column 1) and initial test sets (column 2) aimed at 100% detection of stuck-at faults. Colum 5 shows the final number of equivalence classes obtained after augmentation with additional patterns (column 4) generated by our DTG. On average, the number of equivalence classes increases by 30% with the addition of our DTG tests. For this experiment, every pair of faults was either distinguished or proven to be equivalent for all possible tests, implying that the number of equivalence classes in Table 1 is maximal. In [3], we generated similar results for other fault types and faults derived from real failing ICs by our model independent fault diagnosis methodology [2].