Extraction of Defect Density and Size Distributions from Wafer Sort Test Results

Jeff Nelson

Thomas Zanon

Project

Bridges between non-equipotential regions of an integrated circuit (IC) constitute a significant source of yield loss in nanoscale ICs. The mechanisms that can cause bridge defects are known. However, to conduct sound yield analysis, one must know which portion of the yield loss is due to bridges caused by random contaminations of conducting material and which portion is due to design-process interactions (i.e., systematic defects). For an IC fabricated in a given manufacturing technology, the densities and sizes of random defects affecting process layers can vary. Consequently, an accurate estimation of these defect characteristics is vital for yield learning. Traditionally, process-characterization vehicles such as memories and specialized test structures have been used for estimation. We have proposed a new approach that combines layout information and structural test results to extract defect densities and size distributions (DDSDs) for each metal layer [1]. The proposed strategy does not require the extra cost of designing, fabricating, and testing special test structures. Instead, critical area is extracted for a range of defect sizes for multi-line bridges identified from the layout. Using test results from wafer sort, regression is used to solve for the DDSD values that minimize the difference between measured pass/fail test results and those predicted from a critical area yield model. A significant advantage of this strategy over past approaches is that it is not simply the parameterization of an assumed DDSD, but an extraction of the DDSD curves from the data measured from the tester. The overall flow of the strategy is shown in Figure 1.

Selected Highlights

To demonstrate the viability of our strategy, we performed a simulation experiment using 50,000 identical circuits affected by random defects inserted using a pre-defined DDSD for each affected metal layer [1]. The extracted DDSDs were well-correlated with the pre-defined DDSDs, indicating the approach has promise. The success of the simulation experiment led to a similar one conducted on real silicon chips manufactured in a 0.13µm process. The chip was a test vehicle consisting of many replicated ALUs, each independently testable. Using the approach described here, DDSDs were extracted for all metal layers. Figure 2 shows the DDSD for metal layer 1 with 95% confidence intervals. The confidence intervals for larger defect sizes are too tight to be visible. One can observe that the extracted DDSD follows the power-law (a common model for defect size distributions), where large defects are less likely to occur than smaller defects. The promising results of both the simulation and silicon experiments indicate that our methodology can extract the desired process characteristics. Our ongoing research is currently aimed at improving the accuracy of the extracted results as well as searching for ways to decrease the volume of data that must be collected.