Research
Below are brief descriptions of several currently active research projects within the CM-LIST research group. Please click the links for more in-depth discussion of each project.
Distinguishing Test Generation for Arbitrary Faults
Naresh Bhatti and Shawn Blanton
An automatic test generation tool is developed that can generate tests to distinguish faults of arbitrary types.
Physically-Aware Test
Naresh Bhatti, Yen-Tzu Lin, Osei Poku, and Shawn Blanton
N-detect test sets are generated based on circuit constraints on
signal lines in close physical proximity to a line affected by an
arbitrary defect. Test sets are applied to a 90nm industrial chip.
Statistical Test Compaction
Sounil Biswas and Shawn Blanton
A statistical learning based methodology is developed for eliminating tests for a non-digital device while maintaining the product quality and lowering yield loss.
Testing for Emerging Technologies
Jason Brown and Shawn Blanton
A built-in self-test technique is presented for chemically-assembled electronic nanotechnology circuits.
Automated Standard Cell Library Analysis for Improved Defect Modeling
Jason Brown and Shawn Blanton
A mapping between internal nodes of a standard cell and the
logic level is created. The mapping is used to identify appropriate activation
and error propagation conditions for internal node defects.
Exploiting Regularity for Inductive Fault Analysis
Jason Brown and Shawn Blanton
By performing inductive fault analysis on smaller blocks of regular circuits, the most likely faults can be extracted from even very large designs.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results
Jeff Nelson, Thomas Zanon, Shawn Blanton, and Wojciech Maly
Defect density and size distributions, key parameters to characterize a manufacturing process are extracted using only product IC test results.
Diagnosis-Based Failure Analysis
Osei Poku, Rao Desineni, and Shawn Blanton
Neighborhood-aware diagnosis is used as a preliminary failure analysis
methodology to reduce the time spent in silicon debug.
Built-In Self-Test for MEMS Tunable Capacitor
Xiaochun Yu and Shawn Blanton
A self-test technique is used that electrically analyzes the
mechanical symmetry of a MEMS tunable capacitor (a component of an RF
system) to detect failures due to defects and local fabrication
variations.