Our research work in CM-LIST is focused on enhancing test from
a go/no-go only endeavor to one that provides feedback about the
design, the process, and their interaction. Specifically, we are
developing design- and process-specific test methodologies to
maximize knowledge extraction from the silicon product for meeting
and maintaining yield and quality objectives. Various projects
focus on different aspects of this vision and include:
Distinguishing Test Generation for Arbitrary Faults
An automatic test generation tool is developed that can generate tests to distinguish faults of arbitrary types.
Physically-Aware Test
N-detect test sets are generated based on circuit constraints on
signal lines in close physical proximity to a line affected by an
arbitrary defect. Test sets are applied to a 90nm industrial chip.
Statistical Test Compaction
A statistical learning based methodology is developed for eliminating tests for a non-digital device while maintaining the product quality and lowering yield loss.
Testing for Emerging Technologies
A built-in self-test technique is presented for chemically-assembled electronic nanotechnology circuits.
Automated Standard Cell Library Analysis for Improved Defect Modeling
A mapping between internal nodes of a standard cell and the
logic level is created. The mapping is used to identify appropriate activation
and error propagation conditions for internal node defects.
Exploiting Regularity for Inductive Fault Analysis
By performing inductive fault analysis on smaller blocks of regular circuits, the most likely faults can be extracted from even very large designs.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results
Defect density and size distributions, key parameters to characterize a manufacturing process are extracted using only product IC test results.
Diagnosis-Based Failure Analysis
Neighborhood-aware diagnosis is used as a preliminary failure analysis
methodology to reduce the time spent in silicon debug.
Built-In Self-Test for MEMS Tunable Capacitor
A self-test technique is used that electrically analyzes the
mechanical symmetry of a MEMS tunable capacitor (a component of an RF
system) to detect failures due to defects and local fabrication
variations.