Reunion:
Complexity-Effective Multicore Redundancy
Wednesday December 6, 2006
Hamerschlag Hall D-210
4:30 pm
This is a practice talk for MICRO-39.
Jared Smolens
Carnegie Mellon University
To protect processor logic from soft errors, multicore redundant
architectures execute two copies of a program on separate cores of a chip
multiprocessor (CMP). Maintaining identical instruction streams is
challenging because redundant cores operate independently, yet must still
receive the same inputs (e.g., load values and shared-memory
invalidations). Past proposals strictly replicate load values across two
cores, requiring significant changes to the highly-optimized core.
We make the key observation that, in the common case, both cores load
identical values without special hardware. When the cores do receive
different load values (e.g., due to a data race), the same mechanisms
employed for soft error detection and recovery can correct the
difference. This observation permits designs that relax input
replication, while still providing correct redundant execution. In this
paper, we present Reunion, an execution model that provides relaxed input
replication and preserves the existing memory interface, coherence
protocols, and consistency models. We evaluate a CMP-based implementation
of the Reunion execution model with full-system, cycle-accurate
simulation. We show that the performance overhead of relaxed input
replication is only 5% and 6% for commercial and scientific workloads,
respectively.
Jared Smolens is a PhD candidate in the ECE department at Carnegie
Mellon University, where he is advised by Prof. James Hoe. He received
his BS and MS in ECE from Carnegie Mellon University. His research
interests are in multiprocessor and microprocessor architectures,
fault tolerance, and performance modeling.
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