Building a Synthesizable x86 for FPGA Emulation

Tuesday November 28, 2004
Hamerschlag Hall D-210
4:30 pm

Eriko Nurvitadhi
Carnegie Mellon University

As the most widely-used ISA, x86 is a subject of importance in computer architectural studies. Being able to emulate this ISA on FPGA would be extremely useful for facilitating x86-based studies (e.g. for fast functional warming, architectural explorations, etc). Nevertheless, such emulation requires having a synthesizable x86 HDL model, which is challenging to build due to the complexity of the ISA.

In this talk, I will present an ongoing effort in building an x86 model for FPGA emulation. The talk will focus on the development approach we use to overcome the complexity of the ISA. Following this approach, we currently have (1) a synthesizable x86 functional model that supports a majority of general purpose instructions, and (2) an initial implementation on the Berkeley Emulation Engine 2 (BEE2) FPGA board that runs several SPEC-INT benchmarks under Linux.

Eriko Nurvitadhi is a graduate student in the Electrical and Computer Engineering Department at Carnegie Mellon. He received his BSs, BA, MS, and MBA degrees from Oregon State University. His current research is in the emulation framework for the TRUSS project. His advisor is Prof. James Hoe.