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Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Tuesday November 21, 2006
Hamerschlag Hall D-210
4:30 pm

This is a practice talk for MICRO-39 in December, 2006.

Sangyeun Cho
University of Pittsburgh

Managing distributed L2 caches is a crucial multicore processor design aspect. Conventional design goals include reducing cache access latency (private cache) and reducing on-chip cache misses (shared cache), given the non-uniform cache access latencies. Unlike previously studied hardware-based private and shared cache designs implementing a "fixed" caching policy, our work proposes an OS-microarchitecture approach that is flexible: it can easily implement a wide spectrum of L2 caching policies without complex hardware support. Furthermore, our approach can provide differentiated execution environments to running programs by dynamically controlling data placement and cache sharing degrees. This talk will be based on our paper to appear in MICRO 2006.

Sangyeun Cho has been with the Department of Computer Science at the University of Pittsburgh since 2004. Before joining Pitt, he was a senior engineer and computer architect at Samsung Semiconductor for 5.5 years, where he designed a number of low-power embedded processors and their caches. Cho received a Ph.D. from the University of Minnesota in 2002. His research interests include: computer architecture and software-microarchitecture interactions.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science