A Low-Radix and Low-Diameter 3D Interconnection Network Design
Tuesday November 4, 2008
Hamerschlag Hall D-210
4:30 pm
Jun Yang
University of Pittsburgh
The design of the network-on-chip (NoC) topologies for 3D integrated CMPs
has important distinctions from 2D NoCs or off-chip interconnection
networks. First, current 3D stacking technology allows only vertical
inter-layer links. Hence, there cannot be direct connections between
arbitrary nodes in different layers - the vertical connection topology is
essentially fixed. Second, the 3D NoC is highly constrained by the
complexity and power of routers and links. Hence, low-radix routers are
preferred over high-radix routers for lower power and better heat
dissipation. This implies long network latency due to high hop counts in
network paths.
In this talk, I will introduce a low-diameter 3D network design using
low-radix routers. Our topology leverages long wires to connect remote
intra-layer nodes. We take the advantage of the state-of-the-art one-hop
vertical communication design to utilize the long wires for shortening
network paths. Effectively, we implement a small-to-medium sized clique
network in different layers of a 3D chip. The resulting topology generates a
diameter of 3-hop only network, using routers of less radix than that of a
3D mesh network. The proposed network shows up to 29% of network latency
reduction, up to 10% throughput improvement, and up to 24% energy reduction,
when compared to a 3D mesh network.
Jun Yang is an assistant professor of Electrical and Computer Engineering at
University of Pittsburgh. She obtained her Ph.D. in CS from the University
of Arizona in 2002. Prior to joining Pitt, she was an assistant professor in
Computer Science and Engineering at University of California Riverside from
2002 to 2006. Her research interests include low power microprocessor
design, thermal management, and 3D chip integration. She is a recipient of
NSF CAREER award in 2008.
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