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Flexus: A Line-Usage-Conscious Low Power Cache Memory

Tuesday October 29, 2002
Hamerschlag Hall D-210
4:00 p.m.

Chi Chen

Carnegie Mellon University

Flexus is a hardware-based design for an energy-efficient microprocessor data cache memory. The key component of Flexus is a line usage predictor that monitors cache line usage in relation to memory instructions of executing programs to make line usage predictions. Based on the usage predictions, cache lines can be speculatively maneuvered to achieve energy saving. The simulation results of selected SPEC benchmark applications show that overall, with a mere 1% performance impact, Flexus achieves a savings on bus switching energy of 32%, in additional to nearly a four times reduction of L1 data cache leakage energy.

Chi Chen is a graduate student working in the Computer Architecture Lab at Carnegie Mellon. His current research interests include low power microarchitectures, fault-tolerant microarchitectures, optimizing compilers, Internet security, reconfigurable computing, distributed computing, high-level hardware synthesis, database management systems, self-managing storage systems, simulation-based microarchitecture verification, and real-time embedded systems, as well as wireless networking. Chi was a Research Aide at the National Argonne Laboratory where he co-designed and implemented the Globus Replica Catalog API and Globus Replica Manager. He received his BS in Computer Engineering from the University of Arizona, and was a Sergeant in the Taiwan Army prior to that. Before serving his country, Chi was a Honda, Taiwan sponsored amateur race car driver . His advisor is Professor Babak Falsafi.



Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science