Fast, Full-System, Cycle-Accurate Computer Simulators via Parallelization

Tuesday October 23, 2007
Hamerschlag Hall D-210
4:30 pm

Derek Chiou
University of Texas - Austin

Cycle-accurate simulators of computer systems have traditionally resisted parallelization efforts. In this talk, I will describe FPGA-Accelerated Simulation Technologies (FAST), a methodology that exploits a classic functional/timing simulator partitioning in a novel way to (i) enable parallel execution for improved simulator performance and (ii) increase simulator functionality while (iii) maintaining or even reducing implementation complexity. Our current cycle-accurate-capable prototype runs unmodified x86 applications on x86 Linux and Windows XP at approximately 1.2MIPS today (two to three orders of magnitude faster than industry x86 simulators) and is expected to achieve 10MIPS over time. Such simulators are useful to virtually all computer system simulator users ranging from architects, through RTL designers and verifiers to software developers. Sharing a common simulation/design infrastructure could foster better communication between these groups, potentially resulting in more integrated and better performing hardware and software.

Derek Chiou became an assistant professor at the University of Texas at Austin in January, 2005. His research areas are high performance computer simulation, computer architecture, parallel computing, Internet router architecture and network processors. His research is supported by a Department of Energy Career award, NSF and SRC and donations from Intel, IBM, Xilinx, Freescale, Altera and VMWare. Before coming to UT, Dr. Chiou was a system architect for five years at Avici Systems, a manufacturer of high-end core routers. His responsibilities included leading all of the architectural simulation efforts, overall system architecture and component architecture including a proprietary scalable switch fabric, fabric interface chips and traffic managers. Dr. Chiou received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT. There he was one of two chief architects of the StarT-NG and StarT-Voyager hybrid shared memory/message passing machines.