The Non-linear Path from Ideas to Silicon

Tuesday October 22, 2002
Hamerschlag Hall D-210
4:00 p.m.

Ed Grochowski
Intel

This talk examines the challenges in designing large custom VLSI chips, specifically microprocessors. We look at the design styles and techniques needed to put hundreds of millions of transistors on a chip that meet the required functionality, IPC performance, frequency, power, area, reliability, and schedule. Central to the chip design process is the microarchitect. As a microarchitect and logic designer, the speaker shares his experiences and insights gained during the design of the 486, Pentium, Pentium II, and Itanium microprocessors. We informally evaluate what design styles and techniques work well and what could be improved upon in the future.

Ed is a Principal Engineer with Intel Labs in Santa Clara, California. He received his BSEE degree from University of California at Berkeley in 1985 and his MSEE degree from University of California at Berkeley in 1986. Ed joined Intel in 1986 and worked on the microarchitecture, logic design, and validation of the 486, Pentium, Pentium II, and Itanium microprocessors. He holds 23 patents related to microprocessor design. Ed is currently working on microarchitectural techniques for future Itanium processors.