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RegionScout and Checkpoint Prediction

Monday October 10, 2005
Hamerschlag Hall D-210
4:30 pm

Andreas Moshovos
University of Toronto

The chip multiprocessor is emerging as the architecture of choice for future processors. Accordingly, techniques that improve various attributes of this architecture are now more important than ever. A key mechanism found in multiprocessors is cache coherence. I will be presenting RegionScout, a simple mechanism that improves the bandwidth and power demands of conventional snoop coherence. The key advantages of RegionScout are that: (1) it can be implemented as a layered extension over existing cache coherence implementations, (2) it requires few, simple hardware resources, and (3) it is transparent to software.

In the second part of this talk I will be presenting a technique for improving the scalability and power of dynamically scheduled, superscalar processors. Such processors rely on speculative execution which in turn requires a mechanism for checkpointing and restoring the machine state. Conventional checkpoint allocation naively allocates checkpoints assuming a worst case scenario. Unfortunately, this approach does not scale well. We propose checkpoint prediction for selective checkpoint allocation and demonstrate that it can significantly reduce the complexity and hence improve the scalability of checkpoint mechanisms.

Andreas Moshovos teaches computer architecture at the Electrical and Computer Engineering Department of the University of Toronto. He received the Ph.D. in Computer Sciences from the University of Wisconsin-Madison and the M.Sc. in Computer Science from the University of Crete, Greece.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science