Accelerating Architectural-level, Full-System Multiprocessor Simulations using FPGAs

Tuesday October 2, 2007
Hamerschlag Hall D-210
4:30 pm

Eric Chung
Carnegie Mellon University

An architectural-level, full-system simulator such as Virtutech Simics is a powerful and versatile research enabler for both architectural exploration and advanced OS/compiler development. Its main shortcoming is limited throughput, especially when simulating multicore/multiprocessor systems. In this talk, we present the ProtoFlex simulation architecture for accelerating full-system multiprocessor simulation using FPGAs. In ProtoFlex, only a small set of frequently encountered behaviors are implemented in the FPGA for acceleration while a software-based reference simulator supports the extensive set of infrequent behaviors. Furthermore, the mapping from simulated processors to the FPGA is virtualized using time-multiplexed interleaving so that many processor contexts can be emulated by a single physical pipeline.

In comparison to conventional FPGA emulation, the ProtoFlex approach greatly reduces the FPGA implementation complexity while retaining nearly all of the performance benefit of FPGA emulation. As an instantiation of the ProtoFlex architecture, we have created an FPGA-accelerated simulator for a 16-way symmetric multiprocessing UltraSPARC III server. Our performance evaluations show that FPGA acceleration using one Xilinx Virtex-II XCV2P70 FPGA provides up to a 28x speedup over Simics when executing a variety of applications including a commercial database server.

Eric Chung is a PhD student advised by Professor James C. Hoe in Electrical and Computer Engineering at Carnegie Mellon University. He received his B.S. in EECS from the University of California Berkeley. His research interests are in full-system emulation of multiprocessor systems using FPGAs.