Near-Optimal Bitline Precharging in High-Performance Nanoscale CMOS Caches

Tuesday September 23, 2003
Hamerschlag Hall D-210
4:00 pm

Se-Hyun Yang
Carnegie Mellon University

High-performance nanoscale CMOS caches statically pull up the bitlines in all cache subarrays to hide the bitline charging latency. Unfortunately, such architectures suffer from a large and growing waste of energy from bitline discharge. Recent proposals advocate bitline isolation to reduce bitline discharge by turning off the precharge devices located between the supply voltage and bitlines. In this paper, we quantify, for the first time, the energy and performance trade-off of bitline isolation and study the potential of bitline isolation. Based on them, we propose architectural techniques necessary to capture the full potential of bitline isolation in nanoscale CMOS L1 caches.

Bitline isolation in future CMOS technology can potentially reduce 89% and 90% of bitline discharge for data and instruction caches. In reality, bitline isolation can be most beneficial if the cache identifies and precharges only the subarrays that will be accessed. However, we show that on-demand subarray precharging degrades performance significantly because it is untimely. In this paper, we propose gated precharging that relies on subarray reference locality, which allows for timely and accurate subarray identification. Using a simple hardware mechanism, gated precharging captures the most of the potential and reduces bitline discharge by 83% (for data caches) and 87% (for instruction caches) for the SPEC2000 and Olden benchmarks, with a minimal 1% degradation of performance.

Se-Hyun Yang is now pursuing his doctoral degree in department of Electrical and Computer Engineering at Carnegie Mellon University. He received his B.S. and M.S. from Korea Advanced Institute of Science and Technology. His current research interests focus on power-aware microprocessor and system design, microarchitecture of general-purpose/high-performance microprocessors and nanoscale CMOS technology scaling. His Ph.D. defense is scheduled for November 20th, 2003.