SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling

Thursday May 8, 2003
Hamerschlag Hall D-210
2:00pm

Tom Wenisch
Carnegie Mellon University

Computer architects rely on software simulation to evaluate and validate the functionality and performance of new hardware designs. As computer architecture designs have become more complex, the throughput of simulation models has dropped dramatically: modern cycle-accurate processor simulators are approximately five orders of magnitude slower than the modeled hardware, and RTL-based models are six or more orders of magnitude slower. Because of prohibitive simulation time, researchers often rely on performance estimates from drastically abbreviated instruction execution streams, which fail to correctly capture global variations in program behavior and performance.

In this talk, I present the SMARTS framework for applying statistical sampling theory to the problem of accelerating processor simulation while achieving accurate results. I present conclusions about simulation sampling derived from the theory, the practical problems associated with direct application of these conclusions, and how SMARTS solves these problems. I demonstrate a SMARTS-enabled simulation infrastructure which can estimate performance and energy consumption with an average error of 0.6% and a 35 to 60 x speedup over the baseline cycle-accurate simulation model.

Thomas Wenisch is a second year PhD student in computer architecture, working with Prof. Babak Falsafi. Tom spends his days developing the SimFlex simulation infrastructure, a full-system multiprocessor simulator based on the SMARTS framework and Virtutech's Simics simulation engine.