Automatic Generation of Custom Hardware for DSP Transforms

Tuesday April 25, 2006
Hamerschlag Hall D-210
4:30 pm

Peter A. Milder
Carnegie Mellon University

The SPIRAL project researches techniques for the automatic generation of optimized hardware and software implementations of digital signal processing (DSP) transforms. Inside the SPIRAL framework, knowledge of algorithmic implementations of transforms is symbolically represented as parameterized factorization rules. By choosing rules and parameters in the recursive application of the factorization rules, SPIRAL can enumerate the design space of O(nlog(n)) algorithms with wide varying consequences in hardware or software mappings.

This talk will begin with an overview of the SPIRAL algorithm generation framework. Then I will present recent work on hardware kernel development for the discrete Fourier transform (DFT). A wide range of hardware implementations are possible for the DFT, offering different tradeoffs in throughput, latency and cost. The well-understood structure of DFT algorithms makes possible a fully automatic synthesis framework that can span the viable interesting design choices. I will present such a synthesis framework that starts from formal mathematical formulas of a general class of fast DFT algorithms and produces performance and cost efficient sequential hardware implementations, making design decisions and tradeoffs according to user specified high-level preferences.

This is joint work with Franz Franchetti, James C. Hoe, and Markus Pueschel.

Peter A. Milder is a Ph.D. student at Carnegie Mellon University, where he is advised by Professor James C. Hoe. Peter works in the SPIRAL group at Carnegie Mellon, where he is currently studying formula-driven hardware synthesis of DSP transforms. He received B.S. and M.S. degrees in Electrical and Computer Engineering from Carnegie Mellon in 2004 and 2005, respectively. His research interests include high-level hardware synthesis and digital signal processing.