Constructing a Memory Access Network Architecture for Application Specific Hardware

Tuesday April 19, 2005
Hamerschlag Hall A-306
4:00 pm

Girish Venkataramani
Carnegie Mellon University

High-level synthesis (HLS) tools have shown great potential for generating high-quality circuits in a timely fashion by bridging the semantic gap between high-level abstractions and gate-level implementations. However, a major obstacle to expanding the domain space of synthesizable applications is the presence of arbitrary memory reference patterns in the source specification. For example, pointer aliasing prevents many tools from expanding the subset of synthesizable ANSI-C. In this talk, I will present SOMA, a framework for Synthesizing and Optimizing Memory Access in high-level abstractions. At the core of this framework is a Memory Access Network (MAN) architecture that inherently enforces dynamic ordering-dependencies between memory accesses. The design space of MAN architectures for a given application is large and there are many axes along which the architecture can be optimized. I will discuss our experience with a couple of MAN optimizations that we have performed - one, reducing the synchronization overhead in dynamic memory dependency checking; and two, improving the average throughput and latency of all accesses in the application through dynamic memory-parallelism analysis. SOMA has been fully integrated into the CASH toolflow to automatically generate gate-level structural Verilog from C programs featuring arbitrary pointers.

Girish received his MS in Computer Science from University of California Riverside, and he is currently a 3rd year Phd student in the ECE department at CMU. He is part of the Phoenix reconfigurable computing group led by Seth Goldstein (who is also his advisor). The Phoenix group is researching on a C-to-hardware toolflow, and his focus is on synthesizing (and optimizing) asynchronous circuits from the compiler IR. He also dabbles in related fields like reconfigurable computing, computer architecture, compiler design and circuit synthesis.