Defect Tolerance at the End of the Roadmap

Tuesday April 13, 2004
Hamerschlag Hall D-210
4:00 pm

Mahim Mishra
Carnegie Mellon University

As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In the first part of this talk, I shall examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. I shall summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality. In the second part of this talk, I shall describe an ongoing effort to implement part of this defect tolerance methodology on Xilinx Virtex II-Pro FPGAs.

Mahim Mishra is a graduate student in the Computer Science Department at Carnegie Mellon Univerity. He is part of the Phoenix group led by Prof. Seth Goldstein. His research focuses on defect tolerance in electronic nanotechnology and end-of-the-roadmap CMOS. Specifically, he is working on test strategies for large reconfigurable fabrics made of future-generation technologies, as well as layout algorithms that are scalable and defect-aware. Mahim obtained an undergraduate degree in Computer Science and Engineering from the Indian Institute of Technology, Kanpur in 2001. In his spare time, he likes to listen to soft rock and Hindi music, to dispense free (and unasked for) advice, and to fantasize about ruling the world.