Data Pump and Processing Architecture

Tuesday April 8, 2008
Hamerschlag Hall D-210
4:00 pm

Qian Yu
Carnegie Mellon University

Main memory accesses always experience long latency due to Memory/CPU speed gap and demand-driven access. In many applications, certain specific kernels exhibit deterministic data flow. This characteristic can be used to prefetch data before they are processed and write results back to main memory when necessary.

In this talk, I will present a parameterizable algorithm-specific architecture -Data Pump and Processing Architecture (DPPA). This architecture improves computing and data access performance of specific data-intensive applications. It explicitly manages on-chip memory hierarchy with dedicated software and minimum hardware mechanisms. In this architecture, two dedicated processors separately control data transport flow and computation flow. As a consequence, memory access and computation will be parallelized ideally. I will also introduce the instruction set architecture and programming model of DPPA, and briefly describe the implementation.

Qian Yu is a post-doctor in the Computer Architecture Laboratory and SPIRAL group at Carnegie Mellon University. She received her Ph.D. degree in Electronic Engineering from Chinese Academy of Sciences in 2006 and spent one year as a post-doctor in University of Illinois at Urbana-Champaign. Qian's research interests include VLSI design for high performance computing and multi-processor communication.