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STEPS towards Cache-resident Transaction Processing

Tuesday April 6, 2004
Hamerschlag Hall D-210
4:00 pm

Stavros Harizopoulos
Carnegie Mellon University

Online transaction processing (OLTP) is a multi-billion dollar industry with high-end database servers employing state-of-the-art processors and storage systems to maximize performance. Unfortunately, recent studies have shown that CPUs are far from realizing their maximum intended throughput because of delays in the processor caches. When running OLTP, instruction-related delays in the memory subsystem account for 25 to 40% of the total execution time. In contrast to data, instruction misses cannot be overlapped with out-of-order execution, and instruction caches cannot grow because the slower access time directly affects the processor speed. The challenge is to alleviate the instruction-related delays without increasing the cache size.

In this talk, I will present Steps, a technique that minimizes instruction cache misses in OLTP workloads by multiplexing concurrent transactions and exploiting common code paths. Under Steps, one transaction paves the cache with instructions, while close followers enjoy a nearly miss-free execution. Steps yields up to 96.7% reduction in instruction-cache misses for each additional concurrent transaction, and at the same time eliminates up to 64% of mispredicted branches by loading a repeating execution pattern into the CPU. I will describe the design and implementation of Steps and show microbenchmark and TPC-C results when running Steps on top of the Shore storage manager.

Stavros Harizopoulos is a Ph.D. candidate in the Department of Computer Science at Carnegie Mellon University. He received his Diploma in Electrical and Computer Engineering from the Technical University of Crete, and his MS degree in Computer Science from Carnegie Mellon. Stavros's current research interests are on database system performance, and more specifically on improving the cache behavior of OLTP workloads. His academic advisor is Professor Anastassia Ailamaki.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science