Clustered Multi-Threading: A Platform for Integrated Dynamic Thermal and Reliability Management

Tuesday April 5, 2005
Hamerschlag Hall D-210
4:00 pm

David Albonesi
Cornell University

Clustered processors have long been proposed as a more scalable alternative to monolithic single-threaded cores. In a clustered processor, the back-end resources are partitioned into several (usually identical) clusters. The front-end instruction steering mechanism attempts to balance cluster utilization and inter-cluster communication in directing instructions to the back ends. Years of tuning these steering mechanisms has led to cycle-level performance that rivals monolithic designs. Clustered designs also have the properties of redundancy and flexibility that makes them highly amenable to microarchitecture-level dynamic thermal and reliability management.

In this talk, we discuss Clustered Multi-Threading, a multi-threaded version of a clustered processor, as a potential microarchitecture for future highly scaled technologies. We discuss how CMT processors can provide on-demand thermal relief and added robustness, and we explore several CMT design alternatives, including thread steering policies, and the partitioning and sharing of the L1 data cache. CMT is shown to provide competitive cycle-level performance to SMT with a greatly simplified and more energy-efficient microarchitecture. Finally, we discuss the potential for CMOS-compatible on-chip optics to improve interconnect performance in future large scale multi-CMT designs.

David H. Albonesi is an Associate Professor of Electrical and Computer Engineering at Cornell University and a member of the Computer Systems Laboratory. He received his B.S.E.E. from the University of Massachusetts Amherst in 1982, his M.S.E.E. from Syracuse University in 1986, and his Ph.D. in Electrical and Computer Engineering from the University of Massachusetts Amherst in 1996. Prior to receiving his Ph.D., he held technical and management leadership positions for 10 years at IBM Corporation (1982-86) and Prime Computer, Incorporated (1986-1992). The primary focus of his industry work was on the microarchitecture of low-latency, high-bandwidth memory hierarchies for high performance processors, the design of shared memory multiprocessor systems, and the development and application of architectural evaluation and hardware emulation tools. From 1996-2004, he was a faculty member in ECE at the University of Rochester, where he led the Complexity-Adaptive Processing (CAP) project. His current research interests include adaptive and power-efficient microarchitecture, multithreaded processors, and power-efficient highly-available systems. Dr. Albonesi received a National Science Foundation CAREER Award and IBM Faculty Partnership Awards in 2001, 2002, and 2003. He co-founded the Workshop on Complexity-Effective Design that has been held the last five years at the International Symposium on Computer Architecture and will be held again at ISCA in 2005. He holds seven U.S. patents and is a Senior Member of the IEEE.