Modeling and FPGA Prototyping of an Itanium Architecture

Tuesday March 30, 2004
Hamerschlag Hall D-210
4:00 pm

Roland Wunderlich
Carnegie Mellon University

The primary means of early design evaluation in microprocessor architecture research is software simulation, but simulation-based studies can fail to uncover critical issues related to the final physical implementation. Previous performance-validation efforts with software models have encountered numerous performance differences when compared against hardware implementations. FPGA based prototypes of microarchitectures do not suffer from this problem, and provide other advantages such as relative circuit area and cycle time metrics. I will discuss our on-going effort to prototype an Itanium microarchitecture on a powerful FPGA platform. To conserve time and effort in model development, our microarchitecture model is written in Bluespec, a synthesizable high-level hardware description language.

Roland Wunderlich is a ECE PhD candidate in the Computer Architecture Lab at Carnegie Mellon. He received his BS in Computer Engineering from Rutgers University, and his MS degree from Carnegie Mellon. Roland is advised by Professor James Hoe.