Addressing
Variability in GALS Architectures
Tuesday March 28, 2006
Hamerschlag Hall D-210
4:30 pm
Sebastian Herbert
Carnegie Mellon University
Globally asynchronous, locally synchronous (GALS) architectures have
been proposed as a means of reducing the amount of a processor's power
budget that is used in the clock network. The core is partitioned into
several domains, each of which is clocked independently. This
partitioning also presents opportunities to recover some of the
performance that is lost to variability due to over-design. In this talk
I present two methods for doing so: one which statically attacks
within-die process variability and another which dynamically addresses
thermal variability. The first is predicated on the observation that
each domain has fewer critical paths than the fully synchronous
processor as a whole, shifting the mean of the FMAX distribution towards
higher speeds. The second takes advantage of the fact that the effect of
a thermal hotspot on delay can be isolated to the domain it is in. In
the process, several feedback loops between delay, frequency, power, and
temperature are closed. I will present preliminary results which show
that even naive implementations can bring about modest improvements in
both performance and energy-delay-squared product when compared to a
baseline GALS architecture.
Sebastian is a first-year PhD student working under Diana Marculescu.
His research interests include energy- and variability-aware
architectures and how these are affected by the move to multicore. His
current research focuses on schemes for assigning frequencies and supply
voltages in GALS microprocessors. Sebastian received a BSE in Computer
Engineering and BS in Computer Science from Tulane University in 2005.
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