System-level Timing Analysis and Optimization for Hardware Compilation

Tuesday March 27, 2007
Hamerschlag Hall D-210
4:30 pm

Girish Venkataramani
Carnegie Mellon University

Traditionally, timing analysis in design automation refers to the analysis of register-to-register critical paths and their effect on clock frequency. In this talk, I will describe a system-level perspective to timing analysis based on the modeling of global timing dependencies between circuit events. Based on this model, it is possible to compute a system-wide Global Critical Path (GCP). The GCP crosses register boundaries and highlights the sub-modules within the circuit where most of the execution time is spent. This knowledge, in turn, enables scalability in design optimization, since hardware compilers can now narrow their optimization effort on the most critical regions of the system. The result is a disciplined approach to the creation of efficient heuristic alternatives to hard optimization problems that balance power/performance/area trade-offs faced in system synthesis.

The global timing analysis and optimization framework has been incorporated into CASH, a hardware compiler which synthesizes gate-level implementations of asynchronous circuits from ANSI-C program specifications. In this context, I will first describe a discrete event model used to capture system-level timing properties of these circuits. Next, I will show how the compiler back-end utilizes the timing analysis results in formulating effective polynomial-time heuristics to tackle pipeline optimization and interconnect synthesis problems that are known to be NP-complete. Experimental results reveal that the solutions produced by these heuristics substantially improve system performance, and can often be shown to be optimal.

Girish is a PhD candidate in the ECE department, and is working on an analysis and optimization framework for high-level synthesis. He is part of the Phoenix project, exploring new architectures, design methodologies and compiler flows for future generations of EDA. He is interested in several research areas including compiler optimization flows, computer architecture, asynchronous circuit design and reconfigurable computing.