and Complexity-Effective Spatial Pattern Prediction
Tuesday March 23, 2004
Hamerschlag Hall D-210
Carnegie Mellon University
Recent research suggests that there are large variations in a cache's
spatial usage, both within and across programs. Unfortunately, conventional
caches typically employ fixed cache line sizes to balance the exploitation
of spatial and temporal locality and to avoid prohibitive cache fill
bandwidth demands. The resulting inability of conventional caches to
exploit spatial variations leads to sub-optimal performance and unnecessary
cache power dissipation.
This talk presents the Spatial Pattern Predictor (SPP), a cost-effective
hardware mechanism that accurately predicts reference patterns within
a spatial group, i.e., a contiguous region of data in memory, at runtime.
The key observation enabling an accurate, yet low-cost, SPP design is
that spatial patterns correlate well with instruction addresses and data
reference offsets within a cache line. The SPP requires only a small
amount of predictor memory to store the predicted patterns. The simulation
results of SPEC CPU2000 benchmarks show that: (1) with a modest amount
of predictor memory, the SPP can achieve a prediction coverage of 95%
on average, (2) assuming a 70nm CMOS technology, the SPP helps reduce
leakage energy in the base cache by 41% on average, incurring less than
1% performance degradation, and (3) prefetching spatial groups of up
to 512 bytes using the SPP can improve execution time by as much as 2x.
Chi Chen is a graduate student working in the Computer Architecture
Lab at Carnegie Mellon University. He received his B.S. degree in Computer
Engineering from the University of Arizona. Chi's current research interests
are centered on proactive power-aware memory hierarchies. He is also
seriously interested in making profits from arbitrages in equity markets.
His academic advisor is Professor Babak Falsafi.