Low-Overhead Selective Re-Execution in the Polymorphic TRIPS Processor

Friday March 14, 2003
Hamerschlag Hall 1112
Time TBD

Doug Burger
University of Texas - Austin

In this talk, I will first present an overview of the Polymorphous TRIPS architecture, which addresses the wire delay problem in both the processing core and memory system, permits scalable wide-issue out-of-order performance from 8- to 64-issue, and can be morphed to meet the needs of diverse applications, including single-threaded, multithreaded (server), or data-intensive (scientific, streaming, and signal processing). I will then present a new technique called Speculative Dataflow Traversal that permits extremely efficient recovery from data mis-speculations, permitting simple, efficient, and effectively free partial rollbacks when a data mis-speculation occurs. I will describe how we use it to make the cost of memory disambiguation cheaper, as well as permitting aggressive data value speculation. I will also show how this technique enables new classes of speculation, such as coherence speculation, which can make shared-memory systems to scale to larger levels.

Doug Burger is an Assistant Professor of Computer Sciences at the University of Texas at Austin. He received his Ph.D. in Computer Sciences from the University of Wisconsin-Madison in 1998, after seven years of gorging on tasty Wisconsin cheese. His main research area is computer architecture, and his interests span compilers, operating systems, and emerging technologies. He is co-leader of the TRIPS project at UT-Austin, which is building a system from the microprocessors on up that is targeted at technologies in the 2010 time-frame, and he coaches the UT Marathon Team.