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The PentiumŪ 4 Processor

March 5, 2002 Tuesday
Hamerschlag Hall 1112
4:00 p.m.

Doug M. Carmean

Principal Architect, Intel Corporation

This talk describes the main features and functions of the PentiumŪ 4 processor micro-architecture. We present the front-end of the machine, including its new form of instruction cache called the Execution Trace Cache. We also describe the out-of-order execution engine, including the extremely low latency double-pumped ALU (Arithmetic Logic Unit) that runs at more than 3.4 GHz. We also discuss the memory subsystem, including the very low latency Level 1 data cache that is accessed in just two clock cycles. We then touch on some of the key features that allow the Pentium 4 processor to have outstanding floating-point and multi-media performance. We provide some key performance numbers for this processor, comparing it to the PentiumŪ III processor.

The PentiumŪ 4 processor has 42 million transistors implemented on Intel's 0.18u CMOS process; with six levels of aluminum interconnect. It has a die size of 217 mm2 and it consumes 75 watts of power at 2000 MHz. Its 3.2 GB/second system bus helps provide the high data bandwidths needed to supply data to today and tomorrow's demanding applications. It adds 144 new 128-bit Single Instruction Multiple Data (SIMD) instructions called SSE2 (Streaming SIMD Extension 2) that improve performance for multi-media, content creation, scientific, and engineering applications.

The PentiumŪ 4 micro-architecture was designed to have an even deeper pipeline (about two times the P6 micro-architecture) with even fewer gates of logic per clock cycle to allow an industry-leading clock rate. Compared to the P6 family of processors, the PentiumŪ 4 processor was designed with a greater than 1.6 times higher frequency target for its main clock rate, on the same process technology. This allows it to operate at a much higher frequency than the P6 family of processors on the same silicon process technology. At its introduction in November 2000, the PentiumŪ 4 processor was at 1.5 times the frequency of the PentiumŪ III processor. Over time this frequency delta will increase as the PentiumŪ 4 processor design matures.

Doug Carmean is a Principal Architect with Intel's Desktop Products Group in Oregon. Doug was one of the key architects, responsible for definition of the Intel Pentium 4 processor. He has been with Intel for 13 years, working on IA-32 processors from the 80486 to the Intel Pentium 4 processor and beyond. Prior to joining Intel, Doug worked at ROSS Technology, Sun Microsystems, Cypress Semiconductor and Lattice Semiconductor. Doug enjoys fast cars and scary, Italian motorcycles.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science