Comprehensive Detection of Errors in Multithreaded Memory Systems

Tuesday February 27, 2007
Hamerschlag Hall 1112
4:30 pm

Dan Sorin
Duke University

Multithreaded architectures, including multicore processors and multithreaded uniprocessors, are becoming ubiquitous. Our goal is to detect all possible errors in the memory systems of these machines, without resorting to large amounts of expensive and power-hungry redundancy. Because correct operation of the memory system is defined by the memory consistency model, we can detect errors by checking if the observed memory system behavior deviates from the specified consistency model. We have designed a framework for dynamic verification of memory consistency (DVMC), and this framework applies to all existing commercial consistency models. Our DVMC framework consists of mechanisms to dynamically verify three invariants that we have proven to be equivalent to memory consistency. We have developed an implementation of the framework for the SPARCv9 architecture, and we have experimentally evaluated its performance using full-system simulation of commercial workloads.

Daniel J. Sorin is an assistant professor of Electrical and Computer Engineering and of Computer Science at Duke University. His research interests include dependable computer architecture and system design.

He received a PhD and MS in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award and a Warren Faculty Scholarship at Duke.