EV8: The
Post-ultimate Alpha
Thursday February 27, 2003
Newell-Simon Hall 3305
10:30 AM
Dr. Joel S. Emer
Intel
Through the 1990's the Alpha microprocessors which were designed and
sold first by Digital Equipment Corporation and then by Compaq
Computer Coroporation were widely considered to be the fastest
microprocessors in the market. Recently, however, Compaq decided to
migrate away from Alpha-based system and stopped development of its
next generation Alpha microprocessor, the EV8. Since the EV8 is not
going to be produced, I plan to use this talk to present some of the
design objectives and ideas that were planned for EV8.
One of the key features of the EV8 was to be "simultaneous
multi-threading" or SMT. Over the last few years, this new style of
hardware multithreaded architecture was explored by researchers at
Compaq (then DEC) and at the University of Washington. This technique
allows a single microprocessor to achieve up to 2X throughput
increases at a relatively low implementation cost. Therefore, in the
first part of this talk, I will give some of the motivation for SMT
and an overview of how we had intended to implement it in EV8.
In the second part of the talk I will present an overview of some of
the other characteristics of the design and try to explain the
rational behind some of those design choices. Finally, I will present
some performance estimates of the EV8 CPU.
Dr. Joel S. Emer is an Intel Fellow, Enterprise Platforms Group, and Director
of Microarchitecture Research where he is leading architectural research
efforts for future processors. He holds a Ph.D. in Electrical Engineering from
the University of Illinois, and M.S.E.E. and B.S.E.E. degrees from
Purdue University. Before joining Intel he spent 22 years as a
Digital/Compaq employee, where he worked on processor performance
analysis and performance modeling methodologies for a number of VAX
and Alpha CPUs. He also has researched heterogeneous distributed
systems and networked file systems at DEC and during a three year
sabbatical at MIT. His current research interests include
multithreaded processor organizations, techniques for increased
instruction level parallelism, pipeline organziation, instruction and
data cache organizations, branch prediction schemes, and performance
modeling.
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